Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power Regulation

3D-stacked processor-memory systems stack memory (DRAM banks) directly on top of logic (CPU cores) using chiplet-on-chiplet packaging technology to provide the next-level computing performance in embedded platforms. Stacking, however, severely increases system’s power density without any accompanying increase heat dissipation capacity. Consequently, suffer more severe thermal issues than their non-stacked counterparts. Nevertheless, do inherit (thermal) management knobs from predecessors - namely Dynamic Voltage and Frequency Scaling (DVFS) for cores Low Power Mode (LPM) banks. In context systems, DVFS LPM are performance- power-wise deeply intertwined. Their non-unified independent use results sub-optimal management. The unified remains unexplored. lack implementation simulators hinders real-world representative evaluation a approach. We extend state-of-the-art interval simulator CoMeT with an knob also propose learning-based technique that employ manner. Detailed simulations extended framework show 10.15% average response time improvement PARSEC SPLASH-2 benchmark suites, along widely-used Deep Neural Network (DNN) workloads against 2.5D (ported systems) proposes LPM.